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ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation.

A. Ottaviano, R. Balas, G. Bambini, A. del Vecchio, M. Ciani, D. Rossi, L. Benini, and A. Bartolini. Int. J. Parallel Program., 52 (1): 93-123 (April 2024)

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Assessing the Performance of OpenTitan as Cryptographic Accelerator in Secure Open-Hardware System-on-Chips.E. Parisi, A. Musa, M. Ciani, F. Barchi, D. Rossi, A. Bartolini, and A. Acquaviva. CoRR, (2024)TitanCFI: Toward Enforcing Control-Flow Integrity in the Root-of-Trust.E. Parisi, A. Musa, S. Manoni, M. Ciani, D. Rossi, F. Barchi, A. Bartolini, and A. Acquaviva. CoRR, (2024)Cyber Security aboard Micro Aerial Vehicles: An OpenTitan-based Visual Communication Use Case.M. Ciani, S. Bonato, R. Psiakis, A. Garofalo, L. Valente, S. Sugumar, A. Giusti, D. Rossi, and D. Palossi. ISCAS, page 1-5. IEEE, (2023)ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation.A. Ottaviano, R. Balas, G. Bambini, A. del Vecchio, M. Ciani, D. Rossi, L. Benini, and A. Bartolini. Int. J. Parallel Program., 52 (1): 93-123 (April 2024)ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation.A. Ottaviano, R. Balas, G. Bambini, A. del Vecchio, M. Ciani, D. Rossi, L. Benini, and A. Bartolini. CoRR, (2023)

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation.

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