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TAPA: A Scalable Task-Parallel Dataflow Programming Framework for Modern FPGAs with Co-Optimization of HLS and Physical Design.

L. Guo, Y. Chi, J. Lau, L. Song, X. Tian, M. Khatti, W. Qiao, J. Wang, E. Ustun, Z. Fang, Z. Zhang, and J. Cong. CoRR, (2022)

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Sotetsu Yuzen

Chi Chu

Hsin Chi

Jian Chi

Mei Chi

Other publications of authors with the same name

HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration.J. Li, Y. Chi, and J. Cong. FPGA, page 51-57. ACM, (2020)PASTA: Programming and Automation Support for Scalable Task-Parallel HLS Programs on Modern Multi-Die FPGAs.M. Khatti, X. Tian, Y. Chi, L. Guo, J. Cong, and Z. Fang. FCCM, page 12-22. IEEE, (2023)Design Automation and Optimization for Memory-Bound Application Accelerators.Y. Chi. University of California, Los Angeles, USA, (2021)Callipepla: Stream Centric Instruction Set and Mixed Precision for Accelerating Conjugate Gradient Solver.L. Song, L. Guo, S. Basalama, Y. Chi, R. Lucas, and J. Cong. CoRR, (2022)Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency.L. Guo, J. Lau, Y. Chi, J. Wang, C. Yu, Z. Chen, Z. Zhang, and J. Cong. FPGA, page 311. ACM, (2020)TAPA-CS: Enabling Scalable Accelerator Design on Distributed HBM-FPGAs.N. Prakriya, Y. Chi, S. Basalama, L. Song, and J. Cong. CoRR, (2023)TARO: Automatic Optimization for Free-Running Kernels in FPGA High-Level Synthesis.Y. Choi, Y. Chi, J. Lau, and J. Cong. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (7): 2423-2427 (July 2023)SASA: A Scalable and Automatic Stencil Acceleration Framework for Optimized Hybrid Spatial and Temporal Parallelism on HBM-based FPGAs.X. Tian, Z. Ye, A. Lu, L. Guo, Y. Chi, and Z. Fang. CoRR, (2022)HBM Connect: High-Performance HLS Interconnect for FPGA HBM.Y. kyu Choi, Y. Chi, W. Qiao, N. Samardzic, and J. Cong. FPGA, page 116-126. ACM, (2021)Callipepla: Stream Centric Instruction Set and Mixed Precision for Accelerating Conjugate Gradient Solver.L. Song, L. Guo, S. Basalama, Y. Chi, R. Lucas, and J. Cong. FPGA, page 247-258. ACM, (2023)

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Disambiguation of "Chi, Yuze"

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TAPA: A Scalable Task-Parallel Dataflow Programming Framework for Modern FPGAs with Co-Optimization of HLS and Physical Design.

Please choose a person to relate this publication to

Sotetsu Yuzen

Chi Chu

Hsin Chi

Jian Chi

Mei Chi

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Chi, Yuze"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML TAPA: A Scalable Task-Parallel Dataflow Programming Framework for Modern FPGAs with Co-Optimization of HLS and Physical Design.

Please choose a person to relate this publication to

Sotetsu Yuzen

Chi Chu

Hsin Chi

Jian Chi

Mei Chi

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

TAPA: A Scalable Task-Parallel Dataflow Programming Framework for Modern FPGAs with Co-Optimization of HLS and Physical Design.