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Hardware-Based Real-Time Workload Forensics., , and . IEEE Des. Test, 37 (4): 52-58 (2020)On the identification of modular test requirements for low cost hierarchical test path construction., and . Integr., 40 (3): 315-325 (2007)Multiple-Bit Upset Protection in Microprocessor Memory Arrays Using Vulnerability-Based Parity Optimization and Interleaving., , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (11): 2447-2460 (2015)Guest Editors' Introduction: Special Section on Chips and Architectures for Emerging Technologies and Applications., , and . IEEE Trans. Computers, 60 (4): 450-451 (2011)Nonlinear decision boundaries for testing analog circuits., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 24 (11): 1760-1773 (2005)An Experimentation Platform for On-Chip Integration of Analog Neural Networks: A Pathway to Trusted and Robust Analog/RF ICs., and . IEEE Trans. Neural Networks Learn. Syst., 26 (8): 1721-1734 (2015)TPE: A Hardware-Based TLB Profiling Expert for Workload Reconstruction., , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 11 (2): 292-305 (2021)Demonstrating and Mitigating the Risk of an FEC-Based Hardware Trojan in Wireless Networks., , , , and . IEEE Trans. Inf. Forensics Secur., 14 (10): 2720-2734 (2019)Amplitude-Modulating Analog/RF Hardware Trojans in Wireless Networks: Risks and Remedies., , , , and . IEEE Trans. Inf. Forensics Secur., (2020)Bias Busters: Robustifying DL-based Lithographic Hotspot Detectors Against Backdooring Attacks., , , , , and . CoRR, (2020)