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Soteria: Towards Resilient Integrity-Protected and Encrypted Non-Volatile Memories., , , and . MICRO, page 1214-1226. ACM, (2021)Eliminating microarchitectural dependency from Architectural Vulnerability., and . HPCA, page 117-128. IEEE Computer Society, (2009)Resilient die-stacked DRAM caches., , , and . ISCA, page 416-427. ACM, (2013)Lessons learned from memory errors observed over the lifetime of Cielo., , , , , and . SC, page 43:1-43:12. IEEE / ACM, (2018)Assessing the impact of hard faults in performance components of modern microprocessors., , , and . ICCD, page 207-214. IEEE Computer Society, (2013)Vulnerability analysis of L2 cache elements to single event upsets., , , and . DATE, page 1276-1281. European Design and Automation Association, Leuven, Belgium, (2006)Low-power, low-storage-overhead chipkill correct via multi-line error correction., , , , and . SC, page 24:1-24:12. ACM, (2013)Balancing Performance and Reliability in the Memory Hierarchy., , , and . ISPASS, page 269-279. IEEE Computer Society, (2005)Faults in data prefetchers: Performance degradation and variability., , , , and . VTS, page 1-6. IEEE Computer Society, (2016)A Research Retrospective on AMD's Exascale Computing Journey., , , , , , , , , and 61 other author(s). ISCA, page 81:1-81:14. ACM, (2023)