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A High-Throughput and Scalable Schoolbook Polynomial Multiplier for Accelerating Saber on FPGA Using a Novel Winograd-Based Architecture.

J. Wang, C. Yang, F. Zhang, J. Hou, Y. Meng, S. Xiang, and Y. Su. IEEE Trans. Circuits Syst. II Express Briefs, 71 (4): 2344-2348 (April 2024)

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Meng Meng

Meng Meng Liang

Meng Zhang

Methods and implementations of road-network matchingM. Zhang. TU München, (2009)

Winfried Meng

Nan Meng

Other publications of authors with the same name

WRA-SS: A High-Performance Accelerator Integrating Winograd With Structured Sparsity for Convolutional Neural Networks.C. Yang, Y. Meng, J. Xi, S. Xiang, J. Wang, and K. Mei. IEEE Trans. Very Large Scale Integr. Syst., 32 (1): 164-177 (January 2024)A High-Throughput and Scalable Schoolbook Polynomial Multiplier for Accelerating Saber on FPGA Using a Novel Winograd-Based Architecture.J. Wang, C. Yang, F. Zhang, J. Hou, Y. Meng, S. Xiang, and Y. Su. IEEE Trans. Circuits Syst. II Express Briefs, 71 (4): 2344-2348 (April 2024)POSS-CNN: An Automatically Generated Convolutional Neural Network with Precision and Operation Separable Structure Aiming at Target Recognition and Detection.J. Hou, J. Zhang, Q. Chen, S. Xiang, Y. Meng, J. Wang, C. Lu, and C. Yang. Inf., 14 (11): 604 (2023)Flexible and Efficient Convolutional Acceleration on Unified Hardware Using the Two-Stage Splitting Method and Layer-Adaptive Allocation of 1-D/2-D Winograd Units.C. Yang, Y. Yang, Y. Meng, K. Huo, S. Xiang, J. Wang, and L. Geng. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 43 (3): 919-932 (March 2024)ALSCA: A Large-Scale Sparse CNN Accelerator Using Position-First Dataflow and Input Channel Merging Approach.Y. Meng, S. Xiang, J. Wang, J. Hou, and C. Yang. IEEE Trans. Circuits Syst. II Express Briefs, 71 (7): 3473-3477 (July 2024)A High-Throughput Toom-Cook-4 Polynomial Multiplier for Lattice-Based Cryptography Using a Novel Winograd-Schoolbook Algorithm.J. Wang, C. Yang, F. Zhang, Y. Meng, S. Xiang, and Y. Su. IEEE Trans. Circuits Syst. I Regul. Pap., 71 (1): 359-372 (January 2024)An Efficient CNN Accelerator Achieving High PE Utilization Using a Dense-/Sparse-Aware Redundancy Reduction Method and Data-Index Decoupling Workflow.Y. Meng, C. Yang, S. Xiang, J. Wang, K. Mei, and L. Geng. IEEE Trans. Very Large Scale Integr. Syst., 31 (10): 1537-1550 (October 2023)TCPM: A Reconfigurable and Efficient Toom-Cook-Based Polynomial Multiplier Over Rings Using a Novel Compressed Postprocessing Algorithm.J. Wang, C. Yang, F. Zhang, Y. Meng, and Y. Su. IEEE Trans. Very Large Scale Integr. Syst., 31 (8): 1153-1166 (August 2023)An Efficient Hardware Implementation of Dilated Convolution Using a Novel Channel-Equivalent Decomposition Method.Y. Xia, Y. Meng, S. Xiang, J. Wang, and C. Yang. ICTA, page 172-173. IEEE, (2023)An Efficient and Scalable FHE-Based PDQ Scheme: Utilizing FFT to Design a Low Multiplication Depth Large-Integer Comparison Algorithm.F. Zhang, C. Yang, R. Zong, X. Zheng, J. Wang, and Y. Meng. IEEE Trans. Inf. Forensics Secur., (2024)

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Disambiguation of "Meng, Yishuo"

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A High-Throughput and Scalable Schoolbook Polynomial Multiplier for Accelerating Saber on FPGA Using a Novel Winograd-Based Architecture.

Please choose a person to relate this publication to

Meng Meng

Meng Meng Liang

Meng Zhang

Winfried Meng

Nan Meng

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Meng, Yishuo"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A High-Throughput and Scalable Schoolbook Polynomial Multiplier for Accelerating Saber on FPGA Using a Novel Winograd-Based Architecture.

Please choose a person to relate this publication to

Meng Meng

Meng Meng Liang

Meng Zhang

Winfried Meng

Nan Meng

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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A High-Throughput and Scalable Schoolbook Polynomial Multiplier for Accelerating Saber on FPGA Using a Novel Winograd-Based Architecture.