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EdgeBERT: Optimizing On-Chip Inference for Multi-Task NLP.

T. Tambe, C. Hooper, L. Pentecost, E. Yang, M. Donato, V. Sanh, A. Rush, D. Brooks, and G. Wei. CoRR, (2020)

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Yu-En Lu

Yu Yang

Yang Yu

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EdgeBERT: Sentence-Level Energy Optimizations for Latency-Aware Multi-Task NLP Inference.T. Tambe, C. Hooper, L. Pentecost, T. Jia, E. Yang, M. Donato, V. Sanh, P. Whatmough, A. Rush, D. Brooks and 1 other author(s). MICRO, page 830-844. ACM, (2021)9.8 A 25mm2 SoC for IoT Devices with 18ms Noise-Robust Speech-to-Text Latency via Bayesian Speech Denoising and Attention-Based Sequence-to-Sequence DNN Speech Recognition in 16nm FinFET.T. Tambe, E. Yang, G. Ko, Y. Chai, C. Hooper, M. Donato, P. Whatmough, A. Rush, D. Brooks, and G. Wei. ISSCC, page 158-160. IEEE, (2021)A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors.W. Chen, K. Li, W. Lin, K. Hsu, P. Li, C. Yang, C. Xue, E. Yang, Y. Chen, Y. Chang and 7 other author(s). ISSCC, page 494-496. IEEE, (2018)Trireme: Exploring Hierarchical Multi-Level Parallelism for Domain Specific Hardware Acceleration.G. Zacharopoulos, A. Ejjeh, Y. Jing, E. Yang, T. Jia, I. Brumar, J. Intan, M. Huzaifa, S. Adve, V. Adve and 2 other author(s). CoRR, (2022)Trireme: Exploration of Hierarchical Multi-level Parallelism for Hardware Acceleration.G. Zacharopoulos, A. Ejjeh, Y. Jing, E. Yang, T. Jia, I. Brumar, J. Intan, M. Huzaifa, S. Adve, V. Adve and 2 other author(s). ACM Trans. Embed. Comput. Syst., 22 (3): 53:1-53:23 (2023)OMU: A Probabilistic 3D Occupancy Mapping Accelerator for Real-time OctoMap at the Edge.T. Jia, E. Yang, Y. Hsiao, J. Cruz, D. Brooks, G. Wei, and V. Reddi. DATE, page 909-914. IEEE, (2022)FlexACC: A Programmable Accelerator with Application-Specific ISA for Flexible Deep Neural Network Inference.E. Yang, T. Jia, D. Brooks, and G. Wei. ASAP, page 266-273. IEEE, (2021)A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors.W. Khwa, J. Chen, J. Li, X. Si, E. Yang, X. Sun, R. Liu, P. Chen, Q. Li, S. Yu and 1 other author(s). ISSCC, page 496-498. IEEE, (2018)SM6: A 16nm System-on-Chip for Accurate and Noise-Robust Attention-Based NLP Applications : The 33rd Hot Chips Symposium - August 22-24, 2021.T. Tambe, E. Yang, G. Ko, Y. Chai, C. Hooper, M. Donato, P. Whatmough, A. Rush, D. Brooks, and G. Wei. HCS, page 1-13. IEEE, (2021)A 16-nm SoC for Noise-Robust Speech and NLP Edge AI Inference With Bayesian Sound Source Separation and Attention-Based DNNs.T. Tambe, E. Yang, G. Ko, Y. Chai, C. Hooper, M. Donato, P. Whatmough, A. Rush, D. Brooks, and G. Wei. IEEE J. Solid State Circuits, 58 (2): 569-581 (February 2023)

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Disambiguation of "Yang, En-Yu"

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EdgeBERT: Optimizing On-Chip Inference for Multi-Task NLP.

Please choose a person to relate this publication to

Yu-En Lu

Yu Yang

Yu Yang

Yu Yang

Yang Yu

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Yang, En-Yu"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML EdgeBERT: Optimizing On-Chip Inference for Multi-Task NLP.

Please choose a person to relate this publication to

Yu-En Lu

Yu Yang

Yu Yang

Yu Yang

Yang Yu

Other publications of authors with the same name

Disambiguation

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EdgeBERT: Optimizing On-Chip Inference for Multi-Task NLP.