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Disambiguation of "Sakurai, Takayasu"

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0.5-V Input Digital Low-Dropout Regulator (LDO) with 98.7% Current Efficiency in 65 nm CMOS.

, , , , , , , and . IEICE Trans. Electron., 94-C (6): 938-944 (2011)

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Yoriko Sakurai

Kaneaki Sakurai

Takayasu Shimizu

Miriam Takayasu

 

Other publications of authors with the same name

A 100 Mbps, 4.1 pJ/bit Threshold Detection-Based Impulse Radio UWB Transceiver in 90 nm CMOS., , , , , , , and . IEICE Trans. Electron., 92-C (6): 769-776 (2009)Power Supply Voltage Dependence of Within-Die Delay Variation of Regular Manual Layout and Irregular Place-and-Route Layout., , , , and . IEICE Trans. Electron., 94-C (6): 1072-1075 (2011)Low Power VLSI Circuit Design with Fine-Grain Voltage Engineering., and . IPSJ Trans. Syst. LSI Des. Methodol., (2009)Power distribution analysis of VLSI interconnects using model orderreduction., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 21 (6): 739-745 (2002)High-Speed Searching of Optimum Switching Pattern for Digital Active Gate Drive to Adapt to Various Load Conditions., , , , , , , and . IEEE Trans. Ind. Electron., 69 (5): 5185-5194 (2022)Statistical leakage current reduction in high-leakage environments using locality of block activation in time domain., , and . IEEE J. Solid State Circuits, 39 (9): 1497-1503 (2004)A 6.78-MHz Multiple-Transmitter Wireless Power Transfer System With Efficiency Maximization by Adaptive Magnetic Field Adder IC., , and . IEEE J. Solid State Circuits, 57 (8): 2390-2403 (2022)A super cut-off CMOS (SCCMOS) scheme for 0.5-V supply voltage with picoampere stand-by current., , and . IEEE J. Solid State Circuits, 35 (10): 1498-1501 (2000)A low voltage buck DC-DC converter using on-chip gate boost technique in 40nm CMOS., , , , , , , and . ASP-DAC, page 109-110. IEEE, (2013)An on-chip characterizing system for within-die delay variation measurement of individual standard cells in 65-nm CMOS., , , and . ASP-DAC, page 109-110. IEEE, (2011)