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Disambiguation of "Iizuka, Tetsuya"

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A Tutorial on Systematic Design of CMOS A/D Converters: Illustrated by a 10 b, 500 MS/s SAR ADC with 2 GHz RBW.

, , and . ESSCIRC, page 381-386. IEEE, (2021)

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Tetsuya Takahashi

Hajime Iizuka

Tetsuya Mizutani

Tetsuya Kawata

Tetsuya Takahashi

 

Other publications of authors with the same name

INVITED PAPER: A 4.5-5.4GHz Digital Bang-Bang PLL for Cryogenic Applications., , , , , , , , and . ICTA, page 1-4. IEEE, (2023)A 10-GHz Inductorless Cascaded PLL with Zero-ISF Subsampling Phase Detector Achieving -63-dBc Reference Spur, 175-fs RMS Jitter and -240-dB FOMjitter., , , and . VLSI Technology and Circuits, page 10-11. IEEE, (2022)Digitally-Controlled Compensation Current Injection to ATE Power Supply for Emulation of Customer Environment., , , , , , and . J. Electron. Test., 34 (2): 147-161 (2018)A high frequency resolution Digitally-Controlled Oscillator using single-period switching scheme., , and . ESSCIRC, page 399-402. IEEE, (2011)Embedded tutorial: Test and manufacturability for silicon photonics and 3D integration., and . CICC, page 1. IEEE, (2014)A true 4-cycle lock reference-less all-digital burst-mode CDR utilizing coarse-fine phase generator with embedded TDC., , , , and . CICC, page 1-4. IEEE, (2013)7.5Vmax arbitrary waveform generator with 65nm standard CMOS under 1.2V supply voltage., , , and . CICC, page 1-4. IEEE, (2012)An ultra-wide-range fine-resolution two-step time-to-digital converter with built-in foreground coarse gain calibration., , , and . ICECS, page 231-234. IEEE, (2017)A triangular active charge injection scheme using a resistive current for resonant power supply noise suppression., , , and . ICECS, page 318-321. IEEE, (2017)A 0.0053-mm2 6-bit Fully-Standard-Cell-Based Synthesizable SAR ADC in 65 nm CMOS., , and . NEWCAS, page 1-4. IEEE, (2019)