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Disambiguation of "Luong, Howard C."

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A Single-Chip UHF RFID Reader in 0.18 µm CMOS Process.

, , , , , , , , , , and . IEEE J. Solid State Circuits, 43 (8): 1741-1754 (2008)

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Luong Quy Cuong

Luong Quy Cuong

Phuong Minh Luong

Phuc-Hiep Luong

Howard Nelson

 

Other publications of authors with the same name

A 28-MHz wideband switched-capacitor bandpass filter with transmission zeros for high attenuation., , and . IEEE J. Solid State Circuits, 40 (3): 785-790 (2005)Analysis and Design of Magnetically Tuned W -Band Oscillators., and . IEEE Trans. Very Large Scale Integr. Syst., 30 (6): 732-743 (2022)A 1.5-V 4-GHz dynamic-loading regenerative frequency doubler in a 0.35-μm CMOS process., and . IEEE Trans. Circuits Syst. II Express Briefs, 50 (8): 450-455 (2003)A 2.1-GHz Third-Order Cascaded PLL With Sub-Sampling DLL and Clock-Skew-Sampling Phase Detector., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (7): 2118-2126 (2018)A 0.8-V 4.9-mW 1.2-GHz CMOS Fractional-N Frequency Synthesizer for UHF RFID Readers., and . IEEE Trans. Circuits Syst. I Regul. Pap., 55-I (9): 2505-2513 (2008)An 82-107.6-GHz Integer-N ADPLL Employing a DCO With Split Transformer and Dual-Path Switched-Capacitor Ladder and a Clock-Skew-Sampling Delta-Sigma TDC., and . IEEE J. Solid State Circuits, 54 (2): 358-367 (2019)Ultra-Low-Voltage 20-GHz Frequency Dividers Using Transformer Feedback in 0.18-µm CMOS Process., and . IEEE J. Solid State Circuits, 43 (10): 2293-2302 (2008)A Spur-and-Phase-Noise-Filtering Technique for Inductor-Less Fractional-N Injection-Locked PLLs., , , , and . IEEE J. Solid State Circuits, 52 (8): 2128-2140 (2017)A 1-V 100-MS/s 8-bit CMOS Switched-Opamp Pipelined ADC Using Loading-Free Architecture., , and . IEEE J. Solid State Circuits, 42 (4): 730-738 (2007)0.9mW 7GHz and 1.6mW 60GHz frequency dividers with locking-range enhancement in 0.13µm CMOS., , and . ISSCC, page 96-97. IEEE, (2009)