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Disambiguation of "Giterman, Robert"

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A process compensated gain cell embedded-DRAM for ultra-low-power variation-aware design.

, , , , and . ISCAS, page 1006-1009. IEEE, (2016)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Robert Wille

Towards a design flow for reversible logic. Uni Bremen, (2009)

Robert Klöfkorn

Numerics for evolution equations: a general interface based design concept. Uni Freiburg, (2009)

Robert Braun

Referenzmodellierung: Grundlegung und Evaluation der Technik des Modell-Konfigurationsmanagements. TU Dresden, (2010)

Robert Wagner

Inkrementelle Modellsynchronisation. Uni Paderborn, (2009)

Robert Zangenfeind

Das Bedeutung-Text-Modell: Wörterbuch und Grammatik einer integralen Sprachbeschreibung. Uni München, (2009)
 

Other publications of authors with the same name

Improved Read Access in GC-eDRAM Memory by Dual-Negative Word-Line Technique., , , and . ISCAS, page 1-5. IEEE, (2020)A process compensated gain cell embedded-DRAM for ultra-low-power variation-aware design., , , , and . ISCAS, page 1006-1009. IEEE, (2016)4T Gain-Cell with internal-feedback for ultra-low retention power at scaled CMOS nodes., , , , and . ISCAS, page 2177-2180. IEEE, (2014)Replica Technique for Adaptive Refresh Timing of Gain-Cell-Embedded DRAM., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 61-II (4): 259-263 (2014)Area and Energy-Efficient Complementary Dual-Modular Redundancy Dynamic Memory for Space Applications., , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (2): 502-509 (2017)Ultra miniature offset cancelled bandgap reference with ±0.534% inaccuracy from -10°C to 110°C., , and . ISCAS, page 1-4. IEEE, (2017)Power Analysis Resilient SRAM Design Implemented with a 1% Area Overhead Impedance Randomization Unit for Security Applications., , , , , , , and . ESSCIRC, page 69-72. IEEE, (2019)Live Demonstration: An 800 Mhz Gain-Cell Embedded DRAM in 28 nm CMOS Bulk Process for Approximate Computing Applications., , , , , and . ISCAS, page 1-. IEEE, (2018)Lupulus: A Flexible Hardware Accelerator for Neural Networks., , , and . ICASSP, page 1608-1612. IEEE, (2020)Low-Cost Side-Channel Secure Standard 6T-SRAM-Based Memory With a 1% Area and Less Than 5% Latency and Power Overheads., , , , , , , , and . IEEE Access, (2021)