Author of the publication

Area optimized H.264 Intra prediction architecture for 1080p HD resolution.

, , and . ASAP, page 297-300. IEEE Computer Society, (2010)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Hybrid Working Set Algorithm for SVM Learning With a Kernel Coprocessor on FPGA., , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (10): 2221-2232 (2015)FPGA Based Reconfigurable Coprocessor for Deep Convolutional Neural Network Training., , and . DSD, page 381-388. IEEE Computer Society, (2018)Design of a 32-bit, dual pipeline superscalar RISC-V processor on FPGA., , and . DSD, page 340-343. IEEE, (2020)Network Emulation For Tele-driving Application Development., , , , , , , , , and . COMSNETS, page 109-110. IEEE, (2021)High-Level Synthesis of Geant4 Particle Transport Application for FPGA., and . DSD, page 75-83. IEEE, (2022)Transparent FPGA based device for SQL DDoS mitigation., , and . FPT, page 82-89. IEEE, (2013)A scalable network port scan detection system on FPGA., , and . FPT, page 1-6. IEEE, (2011)Space Efficient Diagonal Linear Space Sequence Alignment., , and . BIBE, page 244-249. IEEE Computer Society, (2010)High Throughput Hardware Acceleration for Image Generation using HLS., and . APCCAS, page 309-313. IEEE, (2023)HD Resolution Intra Prediction Architecture for H.264 Decoder., , and . VLSI Design, page 107-112. IEEE Computer Society, (2012)