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Hardware Signature Designs to Deal with Asymmetry in Transactional Data Sets., , , and . IEEE Trans. Parallel Distributed Syst., 24 (3): 506-519 (2013)Vienna-Fortran/HPF Extensions for Sparse and Irregular Problems and Their Compilation., , , and . IEEE Trans. Parallel Distributed Syst., 8 (10): 1068-1083 (1997)Fast Full-Search Block Matching Algorithm Motion Estimation Alternatives in FPGA., , , , and . FPL, page 1-4. IEEE, (2006)SAD computation based on online arithmetic for motion estimation., , , , and . Microprocess. Microsystems, 30 (5): 250-258 (2006)Enhancing the Parallelization of Sparse Matrices through Dynamic Issues., , and . PDPTA, page 1451-1457. CSREA Press, (1999)On Automatic Parallelization of Irregular Reductions on Scalable Shared Memory Systems., , and . Euro-Par, volume 1685 of Lecture Notes in Computer Science, page 422-429. Springer, (1999)Parallel algorithm for principal components based on Hotelling's iterative procedure., , and . PDP, page 144-149. IEEE, (1993)A compiler tool to predict memory hierarchy performance of scientific codes., , , and . Parallel Comput., 30 (2): 225-248 (2004)Efficient Data Structure and Highly Scalable Algorithm for Total-Viewshed Computation., , , and . IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens., 8 (1): 304-310 (2015)High performance VLSI architecture for the trellis coded quantization., , , and . ICIP (2), page 995-998. IEEE Computer Society, (1996)