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Bit-Balance: Model-Hardware Codesign for Accelerating NNs by Exploiting Bit-Level Sparsity.

, , , , , and . IEEE Trans. Computers, 73 (1): 152-163 (January 2024)

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An Alternative Organization of Defect Map for Defect-Resilient Embedded On-Chip Memories., , , , and . Asia-Pacific Computer Systems Architecture Conference, volume 4697 of Lecture Notes in Computer Science, page 102-113. Springer, (2007)Real-time infrared small target detection network and accelerator design., , , , , and . Integr., (2022)Sense: Model-Hardware Codesign for Accelerating Sparse CNNs on Systolic Arrays., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 31 (4): 470-483 (April 2023)NicePIM: Design Space Exploration for Processing-In-Memory DNN Accelerators with 3D-Stacked-DRAM., , , , , and . CoRR, (2023)GoodFloorplan: Graph Convolutional Network and Reinforcement Learning-Based Floorplanning., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (10): 3492-3502 (2022)Synthesizing Brain-Network-Inspired Interconnections for Large-Scale Network-on-Chips., , , , , , and . CoRR, (2021)A partial memory protection scheme for higher effective yield of embedded memory for video data., , , and . ACSAC, page 1-6. IEEE Computer Society, (2008)An IRAM architecture for image analysis and pattern recognition., , and . ICPR, page 1561-1564. IEEE Computer Society, (1998)DALDet: Depth-Aware Learning Based Object Detection for Autonomous Driving., , , , and . AAAI, page 2229-2237. AAAI Press, (2024)Adaptive Turbulence Channel Equalization Based on Neural Network., , , , , and . ICAIT, page 142-145. IEEE, (2022)