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VTEAM: A General Model for Voltage-Controlled Memristors.

, , , and . IEEE Trans. Circuits Syst. II Express Briefs, 62-II (8): 786-790 (2015)

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Exploiting the on-chip inductance in high-speed clock distribution networks, , and . IEEE Trans. Very Large Scale Integr. Syst., 9 (6): 963--973 (December 2001)Inductance/area/resistance tradeoffs in high performance power distribution grids., and . ISCAS (1), page 101-104. IEEE, (2002)Forward body biased keeper for enhanced noise immunity in domino logic circuits., and . ISCAS (2), page 917-920. IEEE, (2004)Compact substrate models for efficient noise coupling and signal isolation analysis., , , , , and . ISCAS, page 2346-2349. IEEE, (2010)Equivalent rise time for resonance in power/ground noise estimation., , , and . ISCAS, page 2422-2425. IEEE, (2008)Signal waveform characterization in RLC trees., , and . ISCAS (6), page 190-193. IEEE, (1999)Inductive interconnect width optimization for low power., and . ISCAS (5), page 273-276. IEEE, (2003)Circuit Synthesis of Clock Distribution Networks Based on Non-Zero Clock Skew., and . ISCAS, page 175-178. IEEE, (1994)Monotonicity Constraints on Path Delays for Efficient Retiming with Localized Clock Skew and Variable Register Delay., , and . ISCAS, page 1748-1751. IEEE, (1995)Decoupling technique and crosstalk analysis for coupled RLC interconnects., and . ISCAS (2), page 521-524. IEEE, (2004)