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Disambiguation of "Onodera, Hidetoshi"

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A 10.3Gbps translmpedance amplifier with mutually coupled inductors in 0.18-μm CMOS.

, , , , and . ISOCC, page 223-226. IEEE, (2011)

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Kaoru Onodera

Keiichi Onodera

Hidetoshi Yamabe

 

Other publications of authors with the same name

Design methodology of process variation tolerant D-Flip-Flops for low voltage circuit operation., , and . SoCC, page 42-47. IEEE, (2014)Branch-and-Bound Placement for Building Block Layout., , and . DAC, page 433-439. ACM, (1991)Process variation aware D-Flip-Flop design using regression analysis., and . ISQED, page 88-93. IEEE, (2018)Experimental Study on Cell-Base High-Performance Datapath Design., , and . IWLS, page 283-287. (2002)Best ways to use billions of devices on a chip - Error predictive, defect tolerant and error recovery designs., and . ASP-DAC, page 811-812. IEEE, (2008)Impact of random telegraph noise on CMOS logic circuit reliability., , and . CICC, page 1-8. IEEE, (2014)Substrate and phase noise characterization., and . CICC, page 448-449. IEEE, (2005)Sensor Signal Processing Using High-Level Synthesis With a Layered Architecture., , , , , , , , , and 4 other author(s). IEEE Embed. Syst. Lett., 10 (4): 119-122 (2018)Welcome to TSLDM - A New Open-Access Online Journal from IPSJ.. IPSJ Trans. Syst. LSI Des. Methodol., (2008)Layout Generator with Flexible Grid Assignment for Area Efficient Standard Cell., , and . IPSJ Trans. Syst. LSI Des. Methodol., (2015)