Author of the publication

De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs.

, , , and . DATE, page 1370-1373. ACM, (2008)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Optimised OpenCL Workgroup Synthesis for Hybrid ARM-FPGA Devices, and . (2015)Heterogeneous FPGA+GPU Embedded Systems: Challenges and Opportunities., , and . CoRR, (2019)Low overhead DFT using CDFG by modifying controller., , , and . IET Comput. Digit. Tech., 1 (4): 322-333 (2007)SystemC Architectural Transaction Level Modelling for Large NoCs., and . FDL, page 142-147. ECSI, Electronic Chips & Systems design Initiative, (2010)Pipelined Streaming Computation of Histogram in FPGA OpenCL., and . PARCO, volume 32 of Advances in Parallel Computing, page 632-641. IOS Press, (2017)Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC., , , , , , and . IOLTS, page 205-206. IEEE Computer Society, (2007)Task Dispersal Measurement in Dynamic Reconfigurable NoCs., , and . ISVLSI, page 167-172. IEEE Computer Society, (2010)TED+: a data structure for microprocessor verification., , , , and . ASP-DAC, page 567-572. ACM Press, (2005)Reducing Test Power, Time and Data Volume in SoC Testing Using Selective Trigger Scan Architecture., , , and . DFT, page 352-360. IEEE Computer Society, (2003)Simultaneous Multiprocessing on a FPGA+CPU Heterogeneous System-On-Chip., , , , , , and . PARCO, volume 32 of Advances in Parallel Computing, page 677-686. IOS Press, (2017)