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Disambiguation of "Choi, Jung Hwan"

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Profit Aware Circuit Design Under Process Variations Considering Speed Binning.

, , , , and . IEEE Trans. Very Large Scale Integr. Syst., 16 (7): 806-815 (2008)

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Sung-Hwan Choi

Hwan-Ok Jung

Jung-Hwan Kim

Seung Hwan Jung

Jung-Hwan Oh

 

Other publications of authors with the same name

A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process., , , , , , , , , and 37 other author(s). ISSCC, page 206-208. IEEE, (2018)O2C: occasional two-cycle operations for dynamic thermal management in high performance in-order microprocessors., , , and . ISLPED, page 189-192. ACM, (2008)Design technologies for a 1.2V 2.4Gb/s/pin high capacity DDR4 SDRAM with TSVs., , , , , , , , , and 1 other author(s). VLSIC, page 1-2. IEEE, (2014)Design of non-contact 2Gb/s I/O test methods for high bandwidth memory (HBM)., , , , , , , , , and 9 other author(s). A-SSCC, page 169-172. IEEE, (2016)23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme., , , , , , , , , and 27 other author(s). ISSCC, page 390-391. IEEE, (2017)Dual-Loop Two-Step ZQ Calibration for Dynamic Voltage-Frequency Scaling in LPDDR4 SDRAM., , , , , , , , , and 13 other author(s). IEEE J. Solid State Circuits, 53 (10): 2906-2916 (2018)A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution., , , , , , , , , and 9 other author(s). IEEE J. Solid State Circuits, 52 (1): 250-260 (2017)Dynamic Bit-Width Adaptation in DCT: An Approach to Trade Off Image Quality and Computation Energy., , and . IEEE Trans. Very Large Scale Integr. Syst., 18 (5): 787-793 (2010)A 40-Gb/s/pin Low-Voltage POD Single-Ended PAM-4 Transceiver with Timing Calibrated Reset-less Slicer and Bidirectional T-Coil for GDDR7 Application., , , , , , , , , and 13 other author(s). VLSI Technology and Circuits, page 148-149. IEEE, (2022)SQNR-based Layer-wise Mixed-Precision Schemes with Computational Complexity Consideration., , , and . ISCAS, page 234-235. IEEE, (2022)