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Disambiguation of "Fujino, Takeshi"

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High Uniqueness Arbiter-Based PUF Circuit Utilizing RG-DTM Scheme for Identification and Authentication Applications.

, , , , , and . IEICE Trans. Electron., 95-C (4): 468-477 (2012)

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Takeshi Morita

Hiroshi Fujino

Takeshi Morita

Takeshi Imamura

Takeshi Omori

 

Other publications of authors with the same name

The implementation of DES circuit on via-programmable structured ASIC architecture VPEX3., , , , and . VLSI-DAT, page 1-4. IEEE, (2013)Tamper-resistant authentication system with side-channel attack resistant AES and PUF using MDR-ROM., , , , , and . ISCAS, page 1462-1465. IEEE, (2015)Live Demonstration: Hierarchical masked image filtering technology on security-camera for privacy protection., , , and . ISCAS, page 473. IEEE, (2014)Side-channel attack resistant AES cryptographic circuits with ROM reducing address-dependent EM leaks., , , , and . ISCAS, page 2547-2550. IEEE, (2014)Development of LED illumination-based spy photo-prevention system., , , and . GCCE, page 129-130. IEEE, (2015)High Uniqueness Arbiter-Based PUF Circuit Utilizing RG-DTM Scheme for Identification and Authentication Applications., , , , , and . IEICE Trans. Electron., 95-C (4): 468-477 (2012)Adversarial Examples Created by Fault Injection Attack on Image Sensor Interface., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 107 (3): 344-354 (2024)An embedded DRAM with a 143-MHz SRAM interface using a sense-synchronized read/write., , , , , and . IEEE J. Solid State Circuits, 38 (11): 1967-1973 (2003)Placement Tool Dedicated for a Via-Programmable Logic Device VPEX., and . Int. J. Comput. Their Appl., 18 (4): 218-226 (2011)Intra-Masking Dual-Rail Memory on LUT Implementation for SCA-Resistant AES on FPGA., and . ACM Trans. Reconfigurable Technol. Syst., 7 (2): 10:1-10:19 (2014)