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A performance bound analysis of multistage combining networks using a probabilistic model.

, , and . ICS, page 448-457. ACM, (1991)

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A Memory Access Validation Scheme against Payload Injection Attacks., and . RAID, volume 7462 of Lecture Notes in Computer Science, page 107-126. Springer, (2012)Binding Time in Distributed Shared Memories for Generic Patterns of Memory References., and . IEICE Trans. Inf. Syst., 87-D (8): 2148-2151 (2004)A High Throughput Packet-Switching Network with Neural Network Controlled Bypass Queueing and Multiplexing., and . ICPP (1), page 9-12. CRC Press, (1994)Augmenting Branch Predictor to Secure Program Execution., and . DSN, page 10-19. IEEE Computer Society, (2007)An Efficient Hardware Support for Control Data Validation., , and . ASAP, page 409-414. IEEE Computer Society, (2007)Global Bus Design of a Bus-Based COMA Multiprocessor DICE., , , and . ICCD, page 231-240. IEEE Computer Society, (1996)A High-Bandwidth Memory Pipeline for Wide Issue Processors., , and . IEEE Trans. Computers, 50 (7): 709-723 (2001)StackLock with simple FSM., and . EIT, page 46-51. IEEE, (2009)Performance of Multistage Combining Networks., , and . ICPP (1), page 550-553. CRC Press, (1991)Run-Time Support for Detection of Memory Access Violations to Prevent Buffer Overflow Exploits., , and . ISC, volume 2851 of Lecture Notes in Computer Science, page 366-380. Springer, (2003)