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SAR TDC architecture for one-shot timing measurement with full digital implementation.

, , , , , , and . ISPACS, page 462-467. IEEE, (2017)

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Study of multistage digital oscilloscope trigger circuit., , , , , , , and . ISPACS, page 663-668. IEEE, (2017)Architecture of high performance successive approximation time digitizer., , , , , , , , and . ISPACS, page 456-461. IEEE, (2017)SAR TDC architecture for one-shot timing measurement with full digital implementation., , , , , , and . ISPACS, page 462-467. IEEE, (2017)Study of jitter generators for high-speed I/O interface jitter tolerance testing., , , , and . ISPACS, page 468-473. IEEE, (2017)Fine Time Resolution TDC Architectures -Integral and Delta-Sigma Types., , , , , , , and . ASICON, page 1-4. IEEE, (2019)SAR TDC Architecture with Self-Calibration Employing Trigger Circuit., , , , , , , and . ATS, page 94-99. IEEE Computer Society, (2017)Gesture-based control for People Persons with Severe Motor Dysfunction by AAGI., , , , , and . LifeTech, page 63-64. IEEE, (2020)Online management framework for building HVAC systems considering peak shaving and thermal comfort: an experimental study., , , , , , , and . MSCPES@CPSIoTWeek, page 10:1-10:7. ACM, (2021)Gray-code input DAC architecture for clean signal generation., , , , , , , , and . ISPACS, page 669-674. IEEE, (2017)