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A Theory for Co-Scheduling Hardware and Software Pipelines in ASIPs and Embedded Processors.

, , and . Des. Autom. Embed. Syst., 6 (3): 243-275 (2002)

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Dynamic Load Balancers for a Multithreaded Multiprocessor System., , , and . Parallel Process. Lett., 11 (1): 169-184 (2001)The Design and Implementation of TIDeFlow: A Dataflow-Inspired Execution Model for Parallel Loops and Task Pipelining., , , , and . Int. J. Parallel Program., 44 (2): 278-307 (2016)Compiling C for the EARTH multithreaded architecture., , , , , , , and . Int. J. Parallel Program., 25 (4): 305-338 (1997)Self-Avoiding Walks over Adaptive Unstructured Grids., , and . Concurr. Pract. Exp., 12 (2-3): 85-109 (2000)Performance of Interconnection Network in Multithreaded Architectures., , , and . PARLE, volume 817 of Lecture Notes in Computer Science, page 823-826. Springer, (1994)Minimizing communication in rate-optimal software pipelining for stream programs., , , and . CGO, page 210-217. ACM, (2010)Mapping the LU decomposition on a many-core architecture: challenges and solutions., and . Conf. Computing Frontiers, page 71-80. ACM, (2009)A New Framework for Elimination-Based Data Flow Analysis Using DJ Graphs., , and . ACM Trans. Program. Lang. Syst., 20 (2): 388-435 (1998)Multithreaded algorithms for the fast Fourier transform., , , and . SPAA, page 176-185. ACM, (2000)Polytasks: A Compressed Task Representation for HPC Runtimes., , , , and . LCPC, volume 7146 of Lecture Notes in Computer Science, page 268-282. Springer, (2011)