( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
4GHz+ low-latency fixed-point and binary floating-point execution units for the POWER6 processor.

, , , , , , , , и . ISSCC, стр. 1728-1734. IEEE, (2006)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Yuen-Yan Chan

Yuen Hsi Chan

Marvin Yuen

Jenny Yuen

Tak-Hong Yuen

 

Другие публикации лиц с тем же именем

Variability analysis for sub-100 nm PD/SOI CMOS SRAM cell., , , , , и . ESSCIRC, стр. 211-214. IEEE, (2004)Deep submicron design techniques for the 500 MHz IBM S/390 G5 custom microprocessor., , , , , , , , , и 2 other автор(ы). ICCD, стр. 258-263. IEEE Computer Society, (1998)High-Performance CMOS Circuit Techniques for the G-4 S/390 Microprocessor., , , и . ICCD, стр. 247-252. IEEE Computer Society, (1997)A 5.6GHz 64kB Dual-Read Data Cache for the POWER6TM Processor., , , , , , , , , и 2 other автор(ы). ISSCC, стр. 2564-2571. IEEE, (2006)7GHz L1 cache SRAMs for the 32nm zEnterprise™ EC12 processor., , , , , , , , и . ISSCC, стр. 324-325. IEEE, (2013)Circuit and Physical Design of the zEnterprise™ EC12 Microprocessor Chips and Multi-Chip Module., , , , , , , , , и 15 other автор(ы). IEEE J. Solid State Circuits, 49 (1): 9-18 (2014)4.1 22nm Next-generation IBM System z microprocessor., , , , , , , , , и 21 other автор(ы). ISSCC, стр. 1-3. IEEE, (2015)4GHz+ low-latency fixed-point and binary floating-point execution units for the POWER6 processor., , , , , , , , и . ISSCC, стр. 1728-1734. IEEE, (2006)Design SRAMs for burn-in., , , , и . VTS, стр. 164-170. IEEE Computer Society, (1993)IBM eServer z900 high-frequency microprocessor technology, circuits, and design methodology., , , , , , , , , и . IBM J. Res. Dev., 46 (4-5): 631- (2002)