Author of the publication

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

4GHz+ low-latency fixed-point and binary floating-point execution units for the POWER6 processor.

B. Curran, B. McCredie, L. Sigal, E. Schwarz, B. Fleischer, Y. Chan, D. Webber, V. Vaden, and A. Goyal. ISSCC, page 1728-1734. IEEE, (2006)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Yuen-Yan Chan

Yuen Hsi Chan

Marvin Yuen

Jenny Yuen

Tak-Hong Yuen

Other publications of authors with the same name

Dynamic hit logic with embedded 8Kb SRAM in 45nm SOI for the zEnterprise™ processor.A. Pelella, Y. Chan, B. Balakrishnan, P. Patel, D. Rodko, and R. Serton. ISSCC, page 72-73. IEEE, (2011)5.5GHz system z microprocessor and multi-chip module.J. Warnock, Y. Chan, H. Harrer, D. Rude, R. Puri, S. Carey, G. Salem, G. Mayer, Y. Chan, M. Mayo and 13 other author(s). ISSCC, page 46-47. IEEE, (2013)Design of Sub-90 nm Low-Power and Variation Tolerant PD/SOI SRAM Cell Based on Dynamic Stability Metrics.R. Joshi, S. Mukhopadhyay, D. Plass, Y. Chan, C. Chuang, and Y. Tan. IEEE J. Solid State Circuits, 44 (3): 965-976 (2009)A 4.1-ns compact 54×54-b multiplier utilizing sign-select Booth encoders.C. Webb, C. Anderson, L. Sigal, K. Shepard, J. Liptay, J. Warnock, B. Curran, B. Krumm, M. Mayo, P. Camporese and 13 other author(s). IEEE J. Solid State Circuits, 32 (11): 1676-1682 (1997)IBM POWER6 SRAM arrays.D. Plass, and Y. Chan. IBM J. Res. Dev., 51 (6): 747-756 (2007)The Dawn of Predictive Chip Yield Design: Along and Beyond the Memory Lane.R. Joshi, R. Kanj, A. Pelella, A. Tuminaro, and Y. Chan. IEEE Des. Test Comput., 27 (6): 36-45 (2010)A 5.2GHz microprocessor chip for the IBM zEnterprise™ system.J. Warnock, Y. Chan, W. Huott, S. Carey, M. Fee, H. Wen, M. Saccamango, F. Malgioglio, P. Meaney, D. Plass and 17 other author(s). ISSCC, page 70-72. IEEE, (2011)Circuit and Physical Design of the zEnterprise™ EC12 Microprocessor Chips and Multi-Chip Module.J. Warnock, Y. Chan, H. Harrer, S. Carey, G. Salem, D. Malone, R. Puri, J. Zitz, A. Jatkowski, G. Strevig and 15 other author(s). IEEE J. Solid State Circuits, 49 (1): 9-18 (2014)4GHz+ low-latency fixed-point and binary floating-point execution units for the POWER6 processor.B. Curran, B. McCredie, L. Sigal, E. Schwarz, B. Fleischer, Y. Chan, D. Webber, V. Vaden, and A. Goyal. ISSCC, page 1728-1734. IEEE, (2006)Design SRAMs for burn-in.W. Reohr, Y. Chan, D. Plass, A. Pelella, and P. Wu. VTS, page 164-170. IEEE Computer Society, (1993)

BibSonomy

Disambiguation of "Chan, Yuen H."

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

4GHz+ low-latency fixed-point and binary floating-point execution units for the POWER6 processor.

Please choose a person to relate this publication to

Yuen-Yan Chan

Yuen Hsi Chan

Marvin Yuen

Jenny Yuen

Tak-Hong Yuen

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Chan, Yuen H."

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 4GHz+ low-latency fixed-point and binary floating-point execution units for the POWER6 processor.

Please choose a person to relate this publication to

Yuen-Yan Chan

Yuen Hsi Chan

Marvin Yuen

Jenny Yuen

Tak-Hong Yuen

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

4GHz+ low-latency fixed-point and binary floating-point execution units for the POWER6 processor.