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A Parallel Built-in Diagnostic Scheme for Multiple Embedded Memories.

, , , , and . MTDT, page 65-69. IEEE Computer Society, (2004)

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Thermal-Aware Fixed-Outline Floorplanning Using Analytical Models With Thermal-Force Modulation., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 29 (5): 985-997 (2021)A Low-Cost Programmable Memory BIST Design for Multiple Memory Instances., , , , , , and . ITC, page 1. IEEE Computer Society, (2008)Synthesis of Multi-Variable MVL Funtions Using Hybrid Mode CMOS Logic., and . ISMVL, page 35-41. IEEE Computer Society, (1994)Intelligent Policy Selection for GPU Warp Scheduler., , , , and . AICAS, page 302-303. IEEE, (2019)Clock Skew Minimization in Multi-Voltage Mode Designs Using Adjustable Delay Buffers., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 29 (12): 1921-1930 (2010)A Behavior-Level Fault Model for the Closed-Loop Operational Amplifier., , , and . J. Inf. Sci. Eng., 16 (5): 751-766 (2000)Fast Steady-State Thermal Analysis., , , , , and . ISOCC, page 15-16. IEEE, (2018)A fast thermal-aware fixed-outline floorplanning methodology based on analytical models., , , , , , and . ICCAD, page 1:1-1:8. ACM, (2018)Crosstalk Fault Detection for Interconnection Lines Based on Path Delay Inertia Principle., , , and . Asian Test Symposium, page 106-111. IEEE Computer Society, (2005)Value assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs., , , , and . ICCAD, page 535-538. ACM, (2009)