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Parallel current-steering D/A Converters for Flexibility and Smartness., , , , and . ISCAS, page 1465-1468. IEEE, (2007)A 6GS/s 0.5GHz BW continuous-time 2-1-1 MASH ΔΣ modulator with phase-boosted current-mode ELD compensation in 40nm CMOS., , , , , , , and . ESSCIRC, page 491-494. IEEE, (2021)Current-mode multi-path excess loop delay compensation for GHz sampling CT ΣΔ ADCs., , , , , , and . ISCAS, page 1-4. IEEE, (2017)A 1.9 mW 250 MHz Bandwidth Continuous-Time ΣΔ Modulator for Ultra-Wideband Applications., , , , , , , and . ISCAS, page 1-5. IEEE, (2018)9.6 A 5.3GHz 16b 1.75GS/S wideband RF Mixing-DAC achieving IMD<-82dBc up to 1.9GHz., , , , and . ISSCC, page 1-3. IEEE, (2015)A 28-nm CMOS 1 V 3.5 GS/s 6-bit DAC With Signal-Independent Delta-I Noise DfT Scheme., , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (1): 44-53 (2015)A 0.037mm2 1GSps 12b self-calibrated 40nm CMOS DAC cell with SFDR>60dB up to 200MHz and IM3 < - 60dB up to 350MHz., and . ECCTD, page 1-4. IEEE, (2020)32.6 A 76-to-81GHz Direct-Digital 7b 14GS/s Double-Balanced I/Q Mixing-DAC Radar-Waveform Synthesizer., , , , and . ISSCC, page 530-532. IEEE, (2024)An on-chip self-calibration method for current mismatch in D/A converters., , , and . ESSCIRC, page 169-172. IEEE, (2005)A novel output transformer based highly linear RF-DAC architecture., , , , and . ECCTD, page 1-4. IEEE, (2013)