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A general approach for identifying hierarchical symmetry constraints for analog circuit layout.

, , , , , and . ICCAD, page 120:1-120:8. IEEE, (2020)

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GNNIE: GNN Inference Engine with Load-balancing and Graph-Specific Caching., , , and . CoRR, (2021)A general approach for identifying hierarchical symmetry constraints for analog circuit layout., , , , , and . ICCAD, page 120:1-120:8. IEEE, (2020)Learning from Experience: Applying ML to Analog Circuit Design., , , , , , , , , and 2 other author(s). ISPD, page 55. ACM, (2020)Understanding Distance-Dependent Variations for Analog Circuits in a FinFET Technology., , , , , , and . ESSDERC, page 69-72. IEEE, (2023)GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits., , , , , , , , , and . DATE, page 55-60. IEEE, (2020)Automated synthesis of mixed-signal ML inference hardware under accuracy constraints., , , , and . ASPDAC, page 478-483. IEEE, (2024)Machine Learning Techniques in Analog Layout Automation., , , , , , , , , and 3 other author(s). ISPD, page 71-72. ACM, (2021)BeGAN: Power Grid Benchmark Generation Using a Process-portable GAN-based Methodology., , , and . ICCAD, page 1-8. IEEE, (2021)A Multicore GNN Training Accelerator., , , , and . ISLPED, page 1-6. IEEE, (2023)A Unified Engine for Accelerating GNN Weighting/Aggregation Operations, With Efficient Load Balancing and Graph-Specific Caching., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (12): 4844-4857 (December 2023)