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Disambiguation of "Kazeminia, Sarang"

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Improved single-stage kickback-rejected comparator for high speed and low noise flash ADCs.

, , , and . ECCTD, page 1-4. IEEE, (2013)

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Sarang Limaye

Amir Kazeminia

Sarang Suhas Limaye

 

Other publications of authors with the same name

A Wide-Range Low-Jitter PLL Based on Fast-Response VCO and Simplified Straightforward Methodology of Loop Stabilization in Integer-N PLLs., , and . J. Circuits Syst. Comput., 24 (7): 1550104:1-1550104:24 (2015)A low-jitter leakage-free digitally calibrated phase locked loop., and . Comput. Electr. Eng., (2020)Bulk controlled offset cancellation mechanism for single-stage latched comparator., , and . MIXDES, page 174-178. IEEE, (2016)A 800MS/s, 150µV input-referred offset single-stage latched comparator., and . MIXDES, page 119-123. IEEE, (2016)High Speed High Precision voltage-Mode Max and Min Circuits., , and . J. Circuits Syst. Comput., 16 (2): 233-244 (2007)Digitally-assisted gain calibration strategy for open-loop residue amplifiers in pipeline ADCs., and . APCCAS, page 680-683. IEEE, (2016)A foreground-liked continuous-time offset cancellation strategy for open-loop inter-stage amplifiers in high-resolution ADCs., and . Integr., (2018)Improved single-stage kickback-rejected comparator for high speed and low noise flash ADCs., , , and . ECCTD, page 1-4. IEEE, (2013)High-speed low-power Single-Stage latched-comparator with improved gain and kickback noise rejection., , , and . APCCAS, page 216-219. IEEE, (2010)An extendable global clock high-speed binary counter compatible to the FPGA CLBs., , and . MIXDES, page 220-223. IEEE, (2017)