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Countermeasures against fault attacks on software implemented AES: effectiveness and cost., , , , and . WESS, page 7. ACM, (2010)Countermeasures against Branch Target Buffer Attacks., , , and . FDTC, page 75-79. IEEE Computer Society, (2007)Connectivity and performance tradeoffs in the cascade correlation learning architecture., and . IEEE Trans. Neural Networks, 5 (6): 930-935 (1994)Exploring the Feasibility of Low Cost Fault Injection Attacks on Sub-threshold Devices through an Example of a 65nm AES Implementation., , , , , and . RFIDSec, volume 7055 of Lecture Notes in Computer Science, page 48-60. Springer, (2011)Application-Level Fault Tolerance as a Complement to System-Level Fault Tolerance., , , and . J. Supercomput., 16 (1-2): 53-68 (2000)A Combined Design-Time/Test-Time Study of the Vulnerability of Sub-Threshold Devices to Low Voltage Fault Attacks., , , , , and . IEEE Trans. Emerg. Top. Comput., 2 (2): 107-118 (2014)Error Analysis and Detection Procedures for a Hardware Implementation of the Advanced Encryption Standard., , , , and . IEEE Trans. Computers, 52 (4): 492-505 (2003)Does the Sharing of Execution Units Improve Performance/Power of Multicores?, , and . ACM Trans. Embed. Comput. Syst., 14 (1): 17:1-17:24 (2015)Effective analytical delay model for transistor sizing., and . ASP-DAC, page 387-392. ACM Press, (2005)Online Inertia-Based Temperature Estimation for Reliability Enhancement., , and . J. Low Power Electron., 12 (3): 159-171 (2016)