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Optimising power efficiency in trace cache fetch unit., , , and . IET Comput. Digit. Tech., 1 (4): 334-348 (2007)An edge-based heuristic for Steiner routing., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 13 (12): 1563-1568 (1994)Reducing non-deterministic loads in low-power caches via early cache set resolution., , and . Microprocess. Microsystems, 31 (5): 293-301 (2007)Compiler-guided leakage optimization for banked scratch-pad memories., , , and . IEEE Trans. Very Large Scale Integr. Syst., 13 (10): 1136-1146 (2005)The Arithmetic Cube., and . IEEE Trans. Computers, 36 (11): 1342-1348 (1987)Distributed Fault Diagnosis in the Butterfly Parallel Processor., , , and . ICPP (1), page 172-175. Pennsylvania State University Press, (1989)Soft error and energy consumption interactions: a data cache perspective., , , , and . ISLPED, page 132-137. ACM, (2004)Exploiting program hotspots and code sequentiality for instruction cache leakage management., , , , and . ISLPED, page 402-407. ACM, (2003)Estimating influence of data layout optimizations on SDRAM energy consumption., , , , , and . ISLPED, page 40-43. ACM, (2003)Editorial.. ACM Trans. Design Autom. Electr. Syst., 5 (3): 265-266 (2000)