Author of the publication

Yield Forecasting Across Semiconductor Fabrication Plants and Design Generations.

, , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (12): 2120-2133 (2017)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

What we know after twelve years developing and deploying test data analytics solutions., , and . ITC, page 1-8. IEEE, (2016)Harnessing process variations for optimizing wafer-level probe-test flow., , , , , and . ITC, page 1-8. IEEE, (2016)A machine learning approach to fab-of-origin attestation., , , , , and . ICCAD, page 92. ACM, (2016)Harnessing fabrication process signature for predicting yield across designs., , , , , and . ISCAS, page 898-901. IEEE, (2016)Yield prognosis for fab-to-fab product migration., , , , , , and . VTS, page 1-6. IEEE Computer Society, (2015)Predicting die-level process variations from wafer test data for analog devices: A feasibility study., , , , , and . LATW, page 1-6. IEEE Computer Society, (2013)Burn-in reduction using principal component analysis., , and . ITC, page 10. IEEE Computer Society, (2005)Wafer-level process variation-driven probe-test flow selection for test cost reduction in analog/RF ICs., , , , and . VTS, page 1-6. IEEE Computer Society, (2016)Statistical outlier screening as a test solution health monitor., , , and . ITC, page 1-10. IEEE, (2016)Machine Learning-Based Adaptive Outlier Detection for Underkill Reduction in Analog/RF IC Testing., , , , , and . VTS, page 1-7. IEEE, (2023)