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In-Route Pin Access-Driven Placement Refinement for Improved Detailed Routing Convergence., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (3): 784-788 (2022)Wafer Topography-Aware Optical Proximity Correction., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (12): 2747-2756 (2006)Cross-Layer Co-Optimization of Network Design and Chiplet Placement in 2.5-D Systems., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (12): 5183-5196 (2020)Simultaneous Buffer Insertion and Wire Sizing Considering Systematic CMP Variation and Random Leff Variation., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 26 (5): 845-857 (2007)A new methodology for reduced cost of resilience., , and . ACM Great Lakes Symposium on VLSI, page 157-162. ACM, (2014)Multilevel circuit partitioning., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 17 (8): 655-667 (1998)Prim-Dijkstra tradeoffs for improved performance-driven routing tree design., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 14 (7): 890-896 (1995)On wirelength estimations for row-based placement., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 18 (9): 1265-1278 (1999)Optimal partitioners and end-case placers for standard-cell layout., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 19 (11): 1304-1313 (2000)Guest Editorial., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 17 (1): 1-2 (1998)