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Design of a Fault-Tolerant Three-Dimensional Dynamic Random-Access Memory with On-Chip Error-Correcting Circuit.. IEEE Trans. Computers, 42 (12): 1453-1468 (1993)Efficient interconnect modeling by Finite Difference Quadrature methods., and . ISCAS (4), page 592-595. IEEE, (2003)On the implementation of RTD based CNNs., , and . ISCAS (3), page 25-28. IEEE, (2004)Resonant tunnelling diode based QMOS edge triggered flip-flop design., , and . ISCAS (3), page 705-708. IEEE, (2004)A novel technique to improve noise immunity of CMOS dynamic logic circuits., and . DAC, page 900-903. ACM, (2004)A Systolic Architecture for High Speed Hypergraph Partitioning Using a Genetic Algorithm., and . Evo Workshops, volume 956 of Lecture Notes in Computer Science, page 109-126. Springer, (1994)Neural computing for built-in self-repair of embedded memory arrays., and . FTCS, page 480-487. IEEE Computer Society, (1989)On circuit techniques to improve noise immunity of CMOS dynamic logic., and . IEEE Trans. Very Large Scale Integr. Syst., 12 (9): 910-925 (2004)Technology and layout-related testing of static random-access memories., and . J. Electron. Test., 5 (4): 347-365 (1994)Restructuring of square processor arrays by built-in self-repair circuit., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 12 (9): 1255-1265 (1993)