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A 7-Die 3D Stacked 3840×2160@120 fps Motion Estimation Processor.

, , , , and . IEICE Trans. Electron., 100-C (3): 223-231 (2017)

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Merge mode based fast inter prediction for HEVC., , , and . VCIP, page 1-4. IEEE, (2015)A Low-Power VLSI Architecture for HEVC De-Quantization and Inverse Transform., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 99-A (12): 2375-2387 (2016)Approximate-DCT-Derived Measurement Matrices with Row-Operation-Based Measurement Compression and its VLSI Architecture for Compressed Sensing., , , and . IEICE Trans. Electron., 101-C (4): 263-272 (2018)Alternating asymmetric search range assignment for bidirectional motion estimation in H.265/HEVC and H.264/AVC., , and . J. Vis. Commun. Image Represent., 25 (5): 1275-1286 (2014)An independent bandwidth reduction device for HEVC VLSI video system., , , , and . ISCAS, page 609-612. IEEE, (2015)Interlaced asymmetric search range assignment for bidirectional motion estimation., , and . ICIP, page 1557-1560. IEEE, (2012)An area-efficient 4/8/16/32-point inverse DCT architecture for UHDTV HEVC decoder., , , , and . VCIP, page 197-200. IEEE, (2014)A High Performance and Low Bandwidth Multi-Standard Motion Compensation Design for HD Video Decoder., , , , , and . IEICE Trans. Electron., 93-C (3): 253-260 (2010)Low-Power Motion Estimation Processor with 3D Stacked Memory., , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 98-A (7): 1431-1441 (2015)A High Performance HEVC De-Blocking Filter and SAO Architecture for UHDTV Decoder., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 96-A (12): 2612-2622 (2013)