( en | de | ru )

 

Disambiguation of "Fan, Deliang"

Author of the publication

copydeleteadd this publication to your clipboard
Accelerating Bulk Bit-Wise X(N)OR Operation in Processing-in-DRAM Platform.

, and . CoRR, (2019)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Deliang Wang

Deliang Chen

Hua Fan

Fan Zhang

Fan Dai

 

Other publications of authors with the same name

Voltage-Based Concatenatable Full Adder Using Spin Hall Effect Switching., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (12): 2134-2138 (2017)Spin-Transfer Torque Devices for Logic and Memory: Prospects and Perspectives., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 35 (1): 1-22 (2016)Design and Synthesis of Ultra Low Energy Spin-Memristor Threshold Logic., , and . CoRR, (2014)Spin Neurons: A Possible Path to Energy-Efficient Neuromorphic Computers., , and . CoRR, (2013)GraphS: A Graph Processing Accelerator Leveraging SOT-MRAM., , , and . DATE, page 378-383. IEEE, (2019)Hierarchical Temporal Memory Based on Spin-Neurons and Resistive Memory for Energy-Efficient Brain-Inspired Computing., , , and . IEEE Trans. Neural Networks Learn. Syst., 27 (9): 1907-1919 (2016)Artificial Neuron using Ag/2D-MoS2/Au Threshold Switching Memristor., , , , , , , , , and . DRC, page 193-194. IEEE, (2019)FP-IMC: A 28nm All-Digital Configurable Floating-Point In-Memory Computing Macro., , , , , and . ESSCIRC, page 405-408. IEEE, (2023)Gradient-Based Novelty Detection Boosted by Self-Supervised Binary Classification., , , , , , and . AAAI, page 8370-8377. AAAI Press, (2022)Processing-in-Memory Accelerator for Dynamic Neural Network with Run-Time Tuning of Accuracy, Power and Latency., , , and . SoCC, page 117-122. IEEE, (2020)