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Другие публикации лиц с тем же именем

A New Look at Reversible Logic Implementation of Decimal Adder., , , и . SoC, стр. 1-4. IEEE, (2007)Fixed Point Decimal Multiplication Using RPS Algorithm., , , и . ISPA, стр. 343-350. IEEE Computer Society, (2008)Dual Stage Encoding Technique to Minimize Cross Coupling across NoC Links., , , , , и . VDAT, стр. 1-6. IEEE, (2021)High Performance, Low Latency Double Digit Decimal Multiplier on ASIC and FPGA., , и . NaBIC, стр. 1445-1450. IEEE, (2009)Dual-mode RNS based programmable decimation filter for WCDMA and WLANa., , , , и . ISCAS, стр. 952-955. IEEE, (2008)Genetic Algorithm-Based Combinational Logic Synthesis Using Universal Logic Modules., , , и . ESA, стр. 210-215. CSREA Press, (2007)DoLaR: Double Layer Routing for Bufferless Mesh Network-on-Chip., , , , и . TENCON, стр. 400-405. IEEE, (2019)Modelling and Impact Analysis of Push Back Attack in 3D Bufferless Network on Chip., , , и . MCSoC, стр. 426-432. IEEE, (2023)2L-2D Routing for Buffered Mesh Network-on-Chip., , , , , и . VDAT, том 1066 из Communications in Computer and Information Science, стр. 308-320. Springer, (2019)Traffic Aware Deflection Rerouting Mechanism for Mesh Network on Chip., , , , и . VLSI-SoC, стр. 25-30. IEEE, (2018)