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Chip/Package Mechanical Stress Impact on 3-D IC Reliability and Mobility Variations.

, , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 32 (11): 1694-1707 (2013)

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On stress aware active area sizing, gate sizing, and repeater insertion., and . ISPD, page 35-42. ACM, (2009)Editorial: ACM Transactions on Design Automation of Electronics Systems and Beyond., , and . ACM Trans. Design Autom. Electr. Syst., 20 (1): 1:1-1:2 (2014)BoxRouter 2.0: A hybrid and robust global router with layer assignment for routability., , , and . ACM Trans. Design Autom. Electr. Syst., 14 (2): 32:1-32:21 (2009)AENEID: a generic lithography-friendly detailed router based on post-RET data learning and hotspot detection., , , and . DAC, page 795-800. ACM, (2011)High-level synthesis of error detecting cores through low-cost modulo-3 shadow datapaths., , , and . DAC, page 161:1-161:6. ACM, (2015)PASAP: power aware structured ASIC placement., and . ISLPED, page 395-400. ACM, (2010)ELIAD: efficient lithography aware detailed router with compact post-OPC printability prediction., , , and . DAC, page 504-509. ACM, (2008)Accurate Waveform Modeling using Singular Value Decomposition with Applications to Timing Analysis., , , , and . DAC, page 148-153. IEEE, (2007)Machine learning for IC design and technology co-optimization in extreme scaling.. VLSI-DAT, page 1. IEEE, (2018)A High-Performance Triple Patterning Layout Decomposer with Balanced Density., , , , , and . CoRR, (2014)