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Spin based neuron-synapse module for ultra low power programmable computational networks.

, , , and . IJCNN, page 1-7. IEEE, (2012)

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Cache Design with Domain Wall Memory., , , , , , and . IEEE Trans. Computers, 65 (4): 1010-1024 (2016)Membrane-Dependent Neuromorphic Learning Rule for Unsupervised Spike Pattern Detection., , , and . CoRR, (2017)Proposal For Neuromorphic Hardware Using Spin Devices, , , and . CoRR, (2012)A 409 GOPS/W Adaptive and Resilient Domino Register File in 22 nm Tri-Gate CMOS Featuring In-Situ Timing Margin and Error Detection for Tolerance to Within-Die Variation, Voltage Droop, Temperature and Aging., , , , , , and . IEEE J. Solid State Circuits, 51 (1): 117-129 (2016)Data-dependant sense-amplifier flip-flop for low power applications., , , , , , , and . CICC, page 1-4. IEEE, (2010)Membrane-dependent neuromorphic learning rule for unsupervised spike pattern detection., , , and . BioCAS, page 164-167. IEEE, (2016)A framework for simulating hybrid MTJ/CMOS circuits: Atoms to system approach., , and . DATE, page 1443-1446. IEEE, (2012)Energy efficient many-core processor for recognition and mining using spin-based memory., , , , and . NANOARCH, page 122-128. IEEE Computer Society, (2011)Low-power functionality enhanced computation architecture using spin-based devices., , , , , and . NANOARCH, page 129-136. IEEE Computer Society, (2011)25.1 A Fully Synthesizable Distributed and Scalable All-Digital LDO in 10nm CMOS., , , , , , and . ISSCC, page 380-382. IEEE, (2020)