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Effective Evaluation of Multi-core Based Systems.

, , , и . ISPDC, стр. 19-25. IEEE, (2013)

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Nicolau Gonçalves

Claude Nicolau

Stéphane Nicolau

Alexandru Soceanu

Alexandru Lupa

 

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Memory aware compilation through accurate timing extraction., , и . DAC, стр. 316-321. ACM, (2000)New directions in compiler technology for embedded systems (embedded tutorial)., , , и . ASP-DAC, стр. 409-414. ACM, (2001)Author retrospective for a global resource-constrained parallelization technique., и . ICS 25th Anniversary, стр. 7-8. ACM, (2014)Comparative architectural characterization of SPEC CPU2000 and CPU2006 benchmarks on the intel® CoreTM 2 Duo processor., , , , , , и . ICSAMOS, стр. 132-141. IEEE, (2008)Cache-aware partitioning of multi-dimensional iteration spaces., , , , и . SYSTOR, стр. 15. ACM, (2009)Abstract Description of Pointer Data Structures: An Approach for Improving the Analysis and Optimization of Imperative Programs., , и . LOPLAS, 1 (3): 243-260 (1992)Adapting cache line size to application behavior., , , , и . International Conference on Supercomputing, стр. 145-154. ACM, (1999)Performance Characterization of Itanium® 2-Based Montecito Processor., , , , , , и . SPEC Benchmark Workshop, том 5419 из Lecture Notes in Computer Science, стр. 36-56. Springer, (2009)A Compilation and Run-Time Framework for Maximizing Performance of Self-scheduling Algorithms., , , , и . NPC, том 8707 из Lecture Notes in Computer Science, стр. 459-470. Springer, (2014)Enhanced Loop Coalescing: A Compiler Technique for Transforming Non-uniform Iteration Spaces., , и . ISHPC, том 4759 из Lecture Notes in Computer Science, стр. 17-32. Springer, (2005)