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Multiplierless structurally orthogonal block-lifting-based quaternionic paraunitary filter banks with sum-of-powers-of-two coefficients.

, , and . MECO, page 1-4. IEEE, (2017)

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Design and implementation of reversible integer quaternionic paraunitary filter banks on adder-based distributed arithmetic., , and . SPA, page 17-22. IEEE, (2017)Multiplierless structurally orthogonal block-lifting-based quaternionic paraunitary filter banks with sum-of-powers-of-two coefficients., , and . MECO, page 1-4. IEEE, (2017)Embedded distributed arithmetic based quaternions multiplier of paraunitary filter bank for lossless-to-lossy image coding., , and . Microprocess. Microsystems, (2017)2-D non-separable integer implementation of paraunitary filter bank based on the quaternionic multiplier block-lifting structure., and . EUSIPCO, page 1-5. IEEE, (2019)High performance multiplier-less pipelined FPGA architecture for 2-D non-separable quaternionic filter banks., and . SPA, page 42-47. IEEE, (2020)Pipelined block-lifting-based embedded processor for multiplying quaternions using distributed arithmetic., , and . MECO, page 222-225. IEEE, (2016)Structurally orthogonal finite precision FPGA implementation of block-lifting-based quaternionic paraunitary filter banks for L2L image coding., , and . DSP, page 1-5. IEEE, (2017)Design and high-performance hardware architecture for image coding using block-lifting-based quaternionic paraunitary filter banks., , and . MECO, page 193-198. IEEE, (2015)Two-dimensional non-separable quaternionic paraunitary filter banks., , and . SPA, page 120-125. IEEE, (2018)