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A High-Performance Triple Patterning Layout Decomposer with Balanced Density., , , , , and . CoRR, (2014)EPIC: Efficient prediction of IC manufacturing hotspots with a unified meta-classification formulation., , , and . CoRR, (2014)AENEID: a generic lithography-friendly detailed router based on post-RET data learning and hotspot detection., , , and . DAC, page 795-800. ACM, (2011)A high-performance triple patterning layout decomposer with balanced density., , , , , and . ICCAD, page 163-169. IEEE, (2013)Synergistic Topology Generation and Route Synthesis for On-Chip Performance-Critical Signal Groups., , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (6): 1147-1160 (2019)O-Router: an optical routing framework for low power on-chip silicon nano-photonic integration., , , , and . DAC, page 264-269. ACM, (2009)Layout decomposition for triple patterning lithography., , , , and . CoRR, (2014)OIL: a nano-photonics optical interconnect library for a new photonic networks-on-chip architecture., and . SLIP, page 11-18. ACM, (2009)Layout Decomposition for Triple Patterning Lithography., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 34 (3): 433-446 (2015)Layout decomposition for triple patterning lithography., , , , and . ICCAD, page 1-8. IEEE Computer Society, (2011)