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Poise: Balancing Thread-Level Parallelism and Memory System Performance in GPUs Using Machine Learning., , and . HPCA, page 492-505. IEEE, (2019)The effect of channel side information at transmitter on coding complexity., , and . ISIT, page 148. IEEE, (2004)Support for symmetric shadow memory in multiprocessors., and . PADTAD, page 5. ACM, (2008)High-throughput VLSI Implementations of Iterative Decoders and Related Code Construction Problems., , , , and . VLSI Signal Processing, 49 (1): 185-206 (2007)Efficient Sequential Consistency Using Conditional Fences., , and . Int. J. Parallel Program., 40 (1): 84-117 (2012)Address-aware fences., , and . ICS, page 313-324. ACM, (2013)Speculative Optimizations for Parallel Programs on Multicores., and . LCPC, volume 5898 of Lecture Notes in Computer Science, page 323-337. Springer, (2009)Fence Placement for Legacy Data-Race-Free Programs via Synchronization Read Detection., , , and . ACM Trans. Archit. Code Optim., 12 (4): 46:1-46:23 (2016)Architectural support for shadow memory in multiprocessors., and . VEE, page 1-10. ACM, (2009)Hermes: A Fast, Fault-Tolerant and Linearizable Replication Protocol., , , , , , and . ASPLOS, page 201-217. ACM, (2020)ASPLOS 2020 was canceled because of COVID-19..