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Disambiguation of "Jeong, Deog-Kyoon"

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An 8-GHz Octa-Phase Error Corrector With Coprime Phase Comparison Scheme in 40-nm CMOS.

, , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 69 (3): 874-878 (2022)

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Su-Jeong Jeong

Wonrae Jeong

Hyung-Gon Jeong

Hang-Kyun Jeong

Chang-Kyo Jeong

 

Other publications of authors with the same name

A 10-Gb/s, 0.03-mm2, 1.28-pJ/bit Half-Rate Injection-Locked CDR With Path Mismatch Tracking Loop in a 28-nm CMOS Technology., , , , , and . IEEE J. Solid State Circuits, 54 (10): 2812-2822 (2019)A 0.3-1.4 GHz All-Digital Fractional-N PLL With Adaptive Loop Gain Controller., , , , and . IEEE J. Solid State Circuits, 45 (11): 2300-2311 (2010)A Capacitor-Coupled Offset-Canceled Sense Amplifier for DRAMs With Reduced Variation of Decision Threshold Voltage., , , , , and . IEEE J. Solid State Circuits, 55 (8): 2219-2227 (2020)A Programmable On-Chip Reference Oscillator With Slow-Wave Coplanar Waveguide in 14-nm FinFET CMOS., , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 67-II (10): 1834-1838 (2020)A 48 Gb/s PAM-4 Transmitter With 3-Tap FFE Based on Double-Shielded Coplanar Waveguide in 65-nm CMOS., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 67-II (9): 1569-1573 (2020)An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance., , , , and . IEEE J. Solid State Circuits, 35 (3): 377-384 (2000)A 10-Gb/s 6-Vpp differential modulator driver in 65-nm CMOS., , and . ISCAS, page 1869-1872. IEEE, (2014)A Practical Implementation of IEEE 1588-2008 Transparent Clock for Distributed Measurement and Control Systems., and . IEEE Trans. Instrumentation and Measurement, 59 (2): 433-439 (2010)A 10 Gb/s voltage swing level controlled output driver in 65-nm CMOS technology., and . ISOCC, page 53-56. IEEE, (2012)Virtual minimum potential queuing., , and . J. High Speed Networks, 16 (4): 323-339 (2007)