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Disambiguation of "Hsueh, Tzu-Chien"

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A 16 Gb/s four-wire CDMA-based high speed I/O link with transmitter timing adjustment.

, and . CICC, page 1-4. IEEE, (2010)

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Ching-Wen Hsueh

Yi-Ching Hsueh

Chieh Chien

Leo Fong-Ziang Hsueh

Rey-Djin Chien

 

Other publications of authors with the same name

A 1.2-5Gb/s 1.4-2pJ/b serial link in 22nm CMOS with a direct data-sequencing blind oversampling CDR., , , , and . VLSIC, page 350-. IEEE, (2015)A scalable 0.128-to-1Tb/s 0.8-to-2.6pJ/b 64-lane parallel I/O in 32nm CMOS., , , , , , , , , and . ISSCC, page 402-403. IEEE, (2013)A 3×3.8Gb/s four-wire high speed I/O link based on CDMA-like crosstalk cancellation., , and . CICC, page 121-124. IEEE, (2009)An on-die all-digital power supply noise analyzer with enhanced spectrum measurements., , , and . ESSCIRC, page 251-254. IEEE, (2014)A 16 Gb/s four-wire CDMA-based high speed I/O link with transmitter timing adjustment., and . CICC, page 1-4. IEEE, (2010)Random Sampling-and-Averaging Techniques for Single-Photon Arrival-Time Detections in Quantum Applications: Theoretical Analysis and Realization Methodology., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 69 (4): 1452-1465 (2022)ChatGPT at the Speed of Light: Optical Comb-Based Monolithic Photonic-Electronic Linear-Algebra Accelerators., , and . CoRR, (2023)An On-Die All-Digital Power Supply Noise Analyzer With Enhanced Spectrum Measurements., , , and . IEEE J. Solid State Circuits, 50 (7): 1711-1721 (2015)26.4 A 25.6Gb/s differential and DDR4/GDDR5 dual-mode transmitter with digital clock calibration in 22nm CMOS., , , , , , , , , and 3 other author(s). ISSCC, page 444-445. IEEE, (2014)A Scalable 0.128-1 Tb/s, 0.8-2.6 pJ/bit, 64-Lane Parallel I/O in 32-nm CMOS., , , , , , , , , and . IEEE J. Solid State Circuits, 48 (12): 3229-3242 (2013)