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Dynamic two-dimensional parallel simulation technique for high-speed fault simulation on a vector processor., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 9 (8): 868-875 (1990)A 390MHz Single-Chip Application and Dual-Mode Baseband Processor in 90nm Triple-Vt CMOS., , , , , , , , , and 2 other author(s). ISSCC, page 274-602. IEEE, (2007)Square Rooting by Iterative Multiply-Additions., , and . Inf. Process. Lett., 60 (5): 267-269 (1996)A Power Management Scheme Controlling 20 Power Domains for a Single-Chip Mobile Processor., , , , , , , , , and 14 other author(s). ISSCC, page 2210-2219. IEEE, (2006)A 65nm dual-mode baseband and multimedia application processor SoC with advanced power and memory management., , , , , , , and . ASP-DAC, page 535-539. IEEE, (2009)SH-MobileG1: A single-chip application and dual-mode baseband processor., , , , , , , , , and 3 other author(s). Hot Chips Symposium, page 1-24. IEEE, (2006)An 8640 MIPS SoC with Independent Power-Off Control of 8 CPUs and 8 RAMs by An Automatic Parallelizing Compiler., , , , , , , , , and 6 other author(s). ISSCC, page 90-91. IEEE, (2008)Efficient Initial Approximation and Fast Converging Methods for Division and Square Root., , and . IEEE Symposium on Computer Arithmetic, page 2-8. IEEE Computer Society, (1995)3.5 A 40nm flash microcontroller with 0.80µs field-oriented-control intelligent motor timer and functional safety system for next-generation EV/HEV., , , , , , , , , and 2 other author(s). ISSCC, page 58-59. IEEE, (2017)A 65 nm Single-Chip Application and Dual-Mode Baseband Processor With Partial Clock Activation and IP-MMU., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 44 (1): 83-89 (2009)