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Variable-Rate FEC Decoder VLSI Architecture for 400G Rate-Adaptive Optical Communication., , and . ICECS, page 45-48. IEEE, (2019)Custom layout strategy for rectangle-shaped log-depth multiplier reduction tree., , , , , , and . ICECS, page 77-80. IEEE, (2009)Manufacturable nanometer designs using standard cells with regular layout., and . ISQED, page 398-405. IEEE, (2013)Time-domain interconnect characterisation flow for appropriate model segmentation., , and . IET Comput. Digit. Tech., 2 (4): 265-274 (2008)DSP-PP: A Simulator/Estimator of Power Consumption and Performance for Parallel DSP Architectures., , and . Applied Informatics, page 767-772. IASTED/ACTA Press, (2003)Benchmarking of Carrier Phase Recovery Circuits for M-QAM Coherent Systems., and . OFC, page 1-3. IEEE, (2021)Energy-Efficient Soft-Assisted Product Decoders., , , , and . OFC, page 1-3. IEEE, (2019)Fiber-on-Chip: Digital FPGA Emulation of Channel Impairments for Real-Time Evaluation of DSP., and . OFC, page 1-3. IEEE, (2022)Separation and extraction of short-circuit power consumption in digital CMOS VLSI circuits., , and . ISLPED, page 245-249. ACM, (1998)GLMC: interconnect length estimation by growth-limited multifold clustering., , and . ISCAS, page 465-468. IEEE, (2000)