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Efficient nested loop pipelining in high level synthesis using polyhedral bubble insertion.

, , and . FPT, page 1-10. IEEE, (2011)

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Superword level parallelism aware word length optimization., and . DATE, page 1068-1073. IEEE, (2017)Efficient hardware implementation of data-flow parallel embedded systems., , and . ICSAMOS, page 364-371. IEEE, (2012)SpecHLS: Speculative Accelerator Design Using High-Level Synthesis., , and . IEEE Micro, 42 (5): 99-107 (2022)A Reconfigurable Parallel Disk System for Filtering Genomic Banks., , , and . Engineering of Reconfigurable Systems and Algorithms, page 154-166. CSREA Press, (2003)Special Issue on Applied Reconfigurable Computing., and . J. Signal Process. Syst., 94 (9): 847-848 (2022)GeCoS: A framework for prototyping custom hardware design flows., , , , , , , , , and 3 other author(s). SCAM, page 100-105. IEEE Computer Society, (2013)FCCMS and the Memory Wall., and . FCCM, page 329-330. IEEE Computer Society, (2000)Cluster of re-configurable nodes for scanning large genomic banks., , , , , , and . Parallel Comput., 31 (1): 73-96 (2005)Hybrid-DBT: Hardware/Software Dynamic Binary Translation Targeting VLIW., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (10): 1872-1885 (2019)Ultra Low-power FSM for Control Oriented Applications., , and . ISCAS, page 1577-1580. IEEE, (2009)