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Delay and Energy Efficient Data Transmission for On-Chip Buses.

, , , and . ISVLSI, page 355-360. IEEE Computer Society, (2006)

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Minimally buffered single-cycle deflection router., , , and . DATE, page 1-4. European Design and Automation Association, (2014)Delay-efficient bus encoding techniques., , and . Microprocess. Microsystems, 33 (5-6): 365-373 (2009)Concurrent Treaps and Impact of Locking Objects., , and . New Generation Comput., 38 (1): 187-212 (2020)Post-Model Validation of Victim DRAM Caches., , , and . ICCD, page 305-308. IEEE, (2019)SkipCache: application aware cache management for chip multi-processors., , and . IET Comput. Digit. Tech., 9 (6): 293-299 (2015)Universality Results for Some Variants of P Systems., and . WMP, volume 2235 of Lecture Notes in Computer Science, page 237-254. Springer, (2000)Probabilistic Rewriting P Systems.. Int. J. Found. Comput. Sci., 14 (1): 157-166 (2003)FatCBST: Concurrent Binary Search Tree with Fatnodes., , and . HPCC/SmartCity/DSS, page 356-363. IEEE Computer Society, (2017)Scattered refresh: An alternative refresh mechanism to reduce refresh cycle time., , and . ASP-DAC, page 598-603. IEEE, (2014)Exploiting Variable Cycle Transmission for Energy-Efficient On-Chip Interconnect Design., , and . VLSI Design, page 235-241. IEEE Computer Society, (2008)