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A novel VLSI architecture of motion compensation for multiple standards.

, , , and . IEEE Trans. Consumer Electronics, 54 (2): 687-694 (2008)

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A flexible and high-performance hardware video encoder architecture., , , , and . PCS, page 373-376. IEEE, (2012)A high speed and efficient architecture of VLD for AVS HD video decoder., , , and . PCS, page 377-380. IEEE, (2012)An adaptive inter CU depth decision algorithm for HEVC., , , , , , and . VCIP, page 1-4. IEEE, (2015)An Efficient Reference Frame Storage Scheme for H.264 HDTV Decoder., , , and . ICME, page 361-364. IEEE Computer Society, (2006)An Efficient VLSI Architecture for Motion Compensation of AVS HDTV Decoder., , , and . J. Comput. Sci. Technol., 21 (3): 370-377 (2006)An AVS HDTV video decoder architecture employing efficient HW/SW partitioning., , , and . IEEE Trans. Consumer Electronics, 52 (4): 1447-1453 (2006)A Background Modeling Scheme Based on High Efficiency Motion Classification for Surveillance Video Coding., , , , , , and . PCM, volume 8879 of Lecture Notes in Computer Science, page 44-53. Springer, (2014)Fast algorithms and VLSI architecture design for HEVC intra-mode decision., , , , , , , and . J. Real Time Image Process., 12 (2): 285-302 (2016)Part-aware Progressive Unsupervised Domain Adaptation for Person Re-Identification., , , , , , , , and . IEEE Trans. Multim., (2021)Content Adaptive Constraint Based Image Upsampling., , , , and . PCM (2), volume 10736 of Lecture Notes in Computer Science, page 827-837. Springer, (2017)