Author of the publication

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Enabling Efficient Dynamic Resizing of Large DRAM Caches via A Hardware Consistent Hashing Mechanism., , , , , , , , and . CoRR, (2016)Challenges of High-Capacity DRAM Stacks and Potential Directions., , , and . MCHPC@SC, page 4-13. ACM, (2018)A Comparison of Scalable Superscalar Processors., , and . SPAA, page 126-137. ACM, (1999)Quantifying and coping with parametric variations in 3D-stacked microarchitectures., , , , , and . DAC, page 144-149. ACM, (2010)The impact of 3-dimensional integration on the design of arithmetic units., and . ISCAS, IEEE, (2006)Understanding Chiplets Today to Anticipate Future Integration Opportunities and Limits., , and . DATE, page 142-145. IEEE, (2021)Increasing GPU Translation Reach by Leveraging Under-Utilized On-Chip Resources., , , and . MICRO, page 1169-1181. ACM, (2021)Die Stacking (3D) Microarchitecture., , , , , , , , , and 5 other author(s). MICRO, page 469-479. IEEE Computer Society, (2006)A Mostly-Clean DRAM Cache for Effective Hit Speculation and Self-Balancing Dispatch., , , , and . MICRO, page 247-257. IEEE Computer Society, (2012)Adaptive Caches: Effective Shaping of Cache Behavior to Workloads., , and . MICRO, page 385-396. IEEE Computer Society, (2006)