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Disambiguation of "Kuan, Ting-Kuei"

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A 0.43pJ/bit true random number generator.

, , and . A-SSCC, page 33-36. IEEE, (2014)

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Pei Kuang

Kuan Tong

Kuan Yang

M Tingart

Wen-tsi Ting

 

Other publications of authors with the same name

A digital MDLL using switched biasing technique to reduce low-frequency phase noise., , , and . A-SSCC, page 101-104. IEEE, (2016)A Loop Gain Optimization Technique for Integer-N TDC-Based Phase-Locked Loops., and . IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (7): 1873-1882 (2015)A 7-nm FinFET CMOS PLL With 388-fs Jitter and -80-dBc Reference Spur Featuring a Track-and-Hold Charge Pump and Automatic Loop Gain Control., , , and . IEEE J. Solid State Circuits, 55 (4): 1043-1050 (2020)A 0.43pJ/bit true random number generator., , and . A-SSCC, page 33-36. IEEE, (2014)A Subharmonically Injection-Locked PLL With Calibrated Injection Pulsewidth., , and . IEEE Trans. Circuits Syst. II Express Briefs, 62-II (6): 548-552 (2015)A Bang Bang Phase-Locked Loop Using Automatic Loop Gain Control and Loop Latency Reduction Techniques., and . IEEE J. Solid State Circuits, 51 (4): 821-831 (2016)A digital bang-bang phase-locked loop with automatic loop gain control and loop latency reduction., and . VLSIC, page 138-. IEEE, (2015)A Digital Bang-Bang Phase-Locked Loop with Background Injection Timing Calibration and Automatic Loop Gain Control in 7NM FinFET CMOS., , , , , and . VLSI Circuits, page 179-180. IEEE, (2018)A 387.6fs Integrated Jitter and -80dBc Reference Spurs Ring based PLL with Track- and-Hold Charge Pump and Automatic Loop Gain Control in 7nm FinFET CMOS., , , , , and . VLSI Circuits, page 164-. IEEE, (2019)A Subharmonically Injection-Locked All-Digital PLL Without Main Divider., , and . IEEE Trans. Circuits Syst. II Express Briefs, 62-II (11): 1033-1037 (2015)